Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design Using Verilog HDL

Category: Electronics | Posted by raviteja p | Posted on August 24, 2018

Project Files

  1. code, document, waveforms

Reference Papers

[1] K. Tsoumanis, N. Axelos, N. Moshopoulos, G. Zervakis and K. Pekmestzi, “Pre-Encoded Multipliers Based on NonRedundant Radix-4 Signed-Digit Encoding”, IEEE Transactions on Computers, 2015. [2] G. W. Reitwiesner, “Binary arithmetic,” Advances in Computers,vol. 1, pp. 231–308, 1960. [3] K. K. Parhi, VLSI Digital Signal Processing Systems: Design andImplementation. John Wiley & Sons, 2007.

Used Software/Hardware

ModelSim6.4c ,Xilinx 9.1/13.2

Description

Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design Using Verilog HDL

Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design Using Verilog HDL,Digital multipliers are among the most critical arithmetic functional units

Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design Using Verilog HDL

Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design Using Verilog HDL search engine Keywords Thesis 123

  • Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design Using Verilog HDL
  • Efficient Adaptive Hold Logic Aging
  • Aging-Aware Reliable Multiplier Design Using Verilog HDL
  • Project Files
  • Reference Papers
  • Used Software/Hardware
  • Digital multipliers
  • critical arithmetic functional units
  • multiplier
  • negative bias temperature
  • instability effect occurs
  • P-type metal oxide semiconductor transistor
  • multiplier speed
  • high-performance multipliers
  • multiplier design
  • logic circuit
  • Adaptive hold logic
  • Positive bias temperature instability
  • Negative bias temperature instability
  • Reliable multiplier
  • Adaptive hold logic
  • P-type metal oxide semiconductor
  • N-type metal oxide semiconductor

Abstract:

Efficient Adaptive Hold Logic Aging-Aware Reliable Multiplier Design Using Verilog HDL,Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a P-type metal oxide semiconductor transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the P-type metal oxide semiconductor transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an N-type metal oxide semiconductor transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations.

Therefore, it is important to design reliable high-performance multipliers. Here, we propose an aging-aware multiplier design with novel adaptive hold logic circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the adaptive hold logic circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a Non-Redundant Radix-4 Signed Digital Multiplier.

Keywords: Adaptive hold logic, Positive bias temperature instability, Negative bias temperature instability, Reliable multiplier, Adaptive hold logic, P-type metal oxide semiconductor, N-type metal oxide semiconductor.

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